1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device taking in external signals and transferring data in synchronization with a clock signal, and particularly, to a DRAM (Dynamic Random Access Memory) integrated on a semiconductor substrate together with a logic. More particularly, the invention relates to a structure for reducing power consumption of a DRAM operating, in a pseudo manner, as an SRAM (Static Random Access Memory), i.e., a pseudo-SRAM.
2. Description of the Background Art
In recent years, a system LSI having a processor, a memory and others integrated on a single semiconductor chip to implement one system with one semiconductor chip, has been widely used for reducing a system size and required power. In such system LSI, a storage capacity of an on-chip memory has been increased with improvement in function and performance of the system. Conventionally, a high speed SRAM is used as the on-chip memory of the system LSI, and is used as a primary cache memory of a processor supported in the system LSI. As a main storage, an off-chip DRAM is used. As described above, even in the system LSI, a hierarchical structure of the memories is employed for the following reasons. As is well known, a gap in operation frequency between a processor and a DRAM is increasing year after year. Therefore, when the processor directly accesses the DRAM, the processor must wait an increased time for data transmission, and this causes a bottleneck to degrade the system performance.
Thus, localization of data access of the processor is utilized, a high speed SRAM is internally arranged, and a part of a DRAM memory space of the main storage is buffered in the high speed SRAM. The processor accesses the internal SRAM so that the wait time can be reduced and the system performance can be improved. However, when the processor accesses a portion outside the range of the memory space buffered in the internal SRAM, then the following procedure is required. Data buffered in the internal SRAM are transferred to the off-chip DRAM for rewriting (i.e., a copy-back operation is performed), and the data in a new memory space required by the processor are transferred from the DRAM to the internal SRAM to rewrite the data in the memory space buffered in the internal SRAM.
A data bus coupling the system LSI and the off-chip DRAM has a width ranging from 16 bits to 32 bits or so due to restriction on the number of pins of a system LSI package. Therefore, the data transfer must be performed by a relatively small bit width, and data transfer between the internal SRAM and the off-chip DRAM is performed being divided into a plurality of number of times of transferring data. Consequently, the data transfer becomes a bottleneck, which also lowers the system performance.
As a method for overcoming the problem in the system structure with DRAM of a main storage off-chip, recently such an architecture attracts a strong attention that a DRAM is embedded in the system LSI to expand the DRAM data bus width to 256 bits or more, and the data are transferred between the SRAM and the DRAM at a time. This large bus width significantly overcomes the problem associated with the bus bottleneck. However, the processor must be kept in a standby state during a period of data transfer between the SRAM and the DRAM accompanying the hierarchy of the memories. This still lowers the system performance.
As one of measures of overcoming the problem of performance deterioration due to the memory hierarchization, it can be considered to increase the memory capacity of the internal SRAM up to as large as the capacity of the main storage. In the case of a full CMOS structure, an SRAM cell is formed of six MOS transistors (insulated gate field effect transistors). However, a memory cell in the DRAM is generally formed of one capacitor and one MOS transistor. Therefore, the cell area of the SRAM is greater in cell area than the DRAM so that it is impossible with an on-chip SRAM to increase sufficiently the memory capacity of the on-chip memory.
Conversely, with a system structure, in which only a processor and a DRAM are employed, and no SRAM is employed, the system performance deteriorates due to a gap in operation frequency between the processor and the DRAM. For overcoming this, research has been actively conducted on a fast pseudo-SRAM using DRAM memory cells. The fast pseudo-SRAM includes memory cells formed of DRAM cells, but operates similarly to the SRAM when viewed externally. Therefore, a fast memory of a large storage capacity is supported on the system LSI on-chip, to eliminate the hierarchical structure of the memories, for aiming to improve the system performance. The structure of such a pseudo-SRAM is disclosed, e.g., in a prior art reference 1 (Japanese Patent Laying-Open No. 2-87399).
In the pseudo-SRAM disclosed in the prior art reference 1, a chip enable signal /CE is used for an external access control signal, similarly to a conventional SRAM. Further, row and column address signals are applied in parallel, and chip enable signal /CE is activated to internally activate row and column selecting operations in a predetermined sequence.
For refreshing data stored in the DRAM cells, a pin terminal not used in the SRAM or an output enable signal terminal is utilized as an input terminal of a refresh control signal /RFSH.
By toggling chip enable signal /CE, an access cycle is determined, and the row and column accesses are executed in accordance with activation of chip enable signal /CE so that this pseudo-SRAM can be operated similarly to the SRAM when viewed externally.
A fast pseudo-SRAM operates in synchronization with a clock signal, and internally completes activation and deactivation of the row- and column-related circuits in a self-timed manner within one clock cycle.
DRAM cells are arranged in rows and columns. Word lines are arranged corresponding to memory cell rows, respectively, and bit line pairs are arranged corresponding to memory cell columns, respectively. A sense amplifier for sensing, amplifying and latching data of a memory cell is arranged for each bit line pair. When row-related circuitry for row selection operates, a word line arranged corresponding to a row designated by a row address signal is driven to a selected state, and the sense amplifiers sense, amplify and latch the data of the memory cells connected to the selected word line. In this sensing operation, therefore, the sense amplifiers, which are equal in number to the memory cells in one row, operate at the same time.
When the column-related circuitry related to the column selection and data access (write/read of data) operates, a memory cell in a column designated by the column address signal is selected from the memory cells connected to the selected word line, and data access (write/read of the data) is performed. In the column select operation, all the memory cells on the selected word line are not selected. The number of the selected memory cells depends on the number of data bits accessed by the processor (logic) at a time, and thus depends on a width of an external data bus of the pseudo-SRAM. For example, memory cells of 2 K bits are selected in the row select operation, and corresponding sense amplifiers latch the data of the selected memory cells. Then, memory cells (sense amplifiers) of 128 bits are selected, and data access is made.
In the fast pseudo-SRAM, the row and column select operations are completed within one clock cycle. In the operation of successive accessing to the fast pseudo-SRAM, therefore, the sense amplifiers charge and discharge the bit lines in each clock cycle. Therefore, if a selected row includes the memory cells of 2 K bits, 2K sense amplifiers simultaneously perform the charging and discharging operations in parallel. The data bits required by the processor (logic) is, e.g., 128 bits, and the data access is made to 128 sense amplifiers. The other sense amplifiers maintain the latching state with no data access, and merely restore the storage data of the DRAM cells in the corresponding columns. Therefore, the bit lines other than the bit lines accessed for data are also charged or discharged by associated sense amplifiers in each clock cycle, resulting in wastage of current. Particularly, if the above structure is used in a battery-powered device such as a portable device, it is desired to reduce current consumption in view of battery life.
The foregoing prior art reference 1 discloses a structure, in which a test is performed by setting a page mode under a condition of “/RFSH before /CE”, similar to “CAS before RAS” condition of a standard DRAM, in a counter check mode of checking an address counter producing a refresh address. A refresh instructing signal /RFSH is lowered to an L level logical low level), and a word line is activated in accordance with a refresh address provided from an internal address counter. Then, a chip enable signal /CE is set to an L level to set the page mode, and the external column access is activated while maintaining the word line active. In this state, the column access is performed in accordance with an output enable signal /OE or write enable signal /WE. By toggling chip enable signal /CE, the column select operation is performed in accordance with an external column address. Refresh instructing signal /RFSH is set to an H level (logical high level), to complete the page mode operation.
In the structure of the prior art reference 1, a row designated by the refresh address is kept in the selected state, and the columns are successively selected in accordance with external column addresses to perform the data access. The column-related circuitry is tested by utilizing a counter check mode for testing an operation of the refresh address counter.
In the structure of the prior art reference 1, a timing condition, which is inhibited on the specification, is used to set the page mode in the test, for performing the test. A row to be selected is designated by the refresh address generated by the refresh address counter, and cannot be externally designated. Accordingly, this operation manner of the prior art reference 1 cannot be used for the data access in the normal operation mode.
In this prior art reference 1, the data access cycle is determined in accordance with toggling of chip enable signal /CE, and no consideration is given to how to internally activate and deactivate the row- and column-related circuits in a the self-timed manner within each clock cycle in the clock synchronous operations, i.e., operations synchronized with the clock signal.
This prior art stands on the premise that the page mode of changing the column address while fixing the row address could not be inherently supported on the pseudo-SRAM and merely intends to separate the refresh operation and the data input/output operation from each other. No consideration is given to the reduction of the power consumption in the normal operation mode, in which the data access is made, and particularly, in the clock synchronous operation, in which the data access is made in synchronization with the clock signal.